A VLSI Design approach for RISC based MIPS architecture

Proceedings of

International Conference on Pervasive Computing and Communication PCC 2012

"A VLSI DESIGN APPROACH FOR RISC BASED MIPS ARCHITECTURE"

A. Y. DESHMUKH MUNMUN GHOSAL

DOI

10.15224/978-981-07-2579-2-243

Pages

45 - 49

Authors

ISBN

978-981-07-2579-2

Abstract: “This paper describes the design and analysis of the functional units of RISC based MIPS architecture. The functional units includes the Instruction fetch unit, instruction decode unit, execution unit, data memory and control unit. The functions of these modules are implemented by pipeline without any interlocks and are simulated successfully on Modelsim 6.3f and Xilinx 9.2i. It also attempts to achieve high performance with the use of a simplified instruction set.”

Keywords: MIPS, RISC, Pipelining, Memory.

International Conference on Pervasive Computing and Communication PCC 2012

"A VLSI DESIGN APPROACH FOR RISC BASED MIPS ARCHITECTURE"

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