Loading...

Proceedings of

International Conference On Advances In Electronics, Electrical And Computer Science Engineering EEC 2012

"ANALYSIS OF TECHNOLOGY MAPPING ALGORITHM FOR LOGIC OPTIMIZATION OF SYMMETRICAL FPGA ARCHITECTURE THROUGH HYBRID LUTS/PLAS"

SUNIL KR. SINGH M. P. S. BHATIA
DOI
10.15224/978-981-07-2950-9-9952
Pages
527 - 531
Authors
2
ISBN
978-981-07-2950-9

Abstract: “Reconfigurable computing using Field Programmable Devices (FPD) provides a method to utilize the available logic resources on the chip for various computations. The basic ability of reconfigurable computing is to perform computations in hardware to increase performance, while retaining the flexibility of application software. The purpose of this paper is to analysis the effect of technology mapping algorithms on logic density of FPGA devices for reconfigurable computing system using Hybrids of Look up tables (LUTs) from FPGA and Programmable logic arrays (PLAs) from CPLD architectures. LUTs/PLAs are both contributing particular strengths in the area of reconfigurable system design. We identified Hybrid LUTs/PLAs architectures as Hybrid Reconfigurable Computing Architectures (HRCA). The basis of the HRCA is that some parts of digital circuits are well-suited for execution with LUTs, but other for PLAs structures. The technology mapping step converts the user define gate level network in”

Keywords: Technology, Leagal System, mapping

Download PDF