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Proceedings of

International Conference on Advanced Computing, Communication and Networks CCN 2011

"SIMULATION OF LOW POWER ARCHITECTURE OF FINITE STATE MACHINE"

DINESH CHANDRA HIMANI MITTAL SAMPATH KUMAR
DOI
10.15224/978-981-07-1847-3-1027
Pages
49 - 54
Authors
3
ISBN
978-981-07-1847-3-1027

Abstract: “With the predominance of mobile devices, rising energy costs, and an awareness of green practices,power consumption has become a major concern for design engineers. When power consumption is analyzed, it breaks down into two main components: static or leakage power, which occurs naturally when components are idle and powered on; and dynamic power, which is the power consumed when components are switching”

Keywords: FSM Decomposition[1] ,Architectural level [2] ,Sub finite state machines , Decoder circuitry , Power consumption

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